Автор Тема: Сборка ванильного u-boot  (Прочитано 709 раз)

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Оффлайн OlegSL

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Сборка ванильного u-boot
« : 08 Апрель, 2019, 10:53:53 »
Хочу собрать современное ванильный u-boot (v2019.04). Делаю следующие команды:
export ARCH=arm
export PATH=/opt/gcc-linaro-7.4.1-2019.02-x86_64_arm-linux-gnueabi/bin/:$PATH
export CROSS_COMPILE=arm-linux-gnueabi-

make mrproper
make mrproper O=/tmp
make mx28evk_config O=/tmp
make -j $(nproc) O=/tmp u-boot.sb
/tmp/tools/mxsboot sd /tmp/u-boot.sb /mnt/u-boot.sb

Флешку подготовил согласно инструкции раздел 3.

Но после установки не может загрузиться. Запускается SPL, но не переходит на загрузку основной части кода U-Boot.
HTLLCSPL: Serial Console Initialised
SPL: Initialising Power Block
SPL: Switching CPU clock to 24MHz XTAL
SPL: Setting auto-restart bit
SPL: Setting VDDD 25mV below DC-DC converters
SPL: Setting VDDA 25mV below DC-DC converters
SPL: Setting VDDIO 25mV below DC-DC converters
SPL: Starting 5V input detection comparator
SPL: Starting battery voltage measurement logic
SPL: Initialisating LRADC
SPL: Enabling LRADC battery measurement
SPL: LRADC channel 7 is present - configuring
SPL: LRADC channel 7 configuration complete
SPL: Configuring power source
SPL: Using default DC-DC clocksource
SPL: Pre-Configuring power block
SPL: Battery Voltage = 1888mV
SPL: Battery Voltage = 1888mV
SPL: Battery Voltage = 4192mV
SPL: Battery Voltage too high
SPL: Configuring power block to boot from 5V input
SPL: 5V VDD good
SPL: Booting from 5V supply
SPL: Powering up 4P2 regulator
SPL: Configuring common 4P2 regulator params
SPL: Enabling 4P2 regulator
SPL: Charging 4P2 capacitor
SPL: Disabling 4P2 DC-DC Input
SPL: Setting 4P2 brownout level
SPL: Battery Voltage = 0mV
SPL: Switching DC-DC converters to 4P2
SPL: Enabling 4P2 DC-DC Input
SPL: 4P2 regulator powered-up
SPL: Switching CPU core clock source to PLL
SPL: Initialising battery brown-out level to 3.0V
SPL: Switching VDDD to DC-DC converters
SPL: Enabling output rail protection
SPL: Setting VDDIO to 3V3 (brownout @ 3v15)
SPL: Setting VDDD to 1V5 (brownout @ 1v315)
SPL: Initialising FRAC0
SPL: FRAC0 Initialised
SPL: Configuring VDDA
SPL: Initialising mx28 SDRAM Controller
SPL: Setting mx28 board specific SDRAM parameters
SPL: Applying SDRAM parameters
SPL: Setting CPU and HBUS clock frequencies
L0x8050100b
0x80502008
          HTLLCSPL: Serial Console Initialised
SPL: Initialising Power Block
SPL: Switching CPU clock to 24MHz XTAL
SPL: Setting auto-restart bit
SPL: Setting VDDD 25mV below DC-DC converters
SPL: Setting VDDA 25mV below DC-DC converters
SPL: Setting VDDIO 25mV below DC-DC converters
SPL: Starting 5V input detection comparator
SPL: Starting battery voltage measurement logic
SPL: Initialisating LRADC
SPL: Enabling LRADC battery measurement
SPL: LRADC channel 7 is present - configuring
SPL: LRADC channel 7 configuration complete
SPL: Configuring power source
SPL: Using default DC-DC clocksource
SPL: Pre-Configuring power block
SPL: Battery Voltage = 1888mV
SPL: Battery Voltage = 1888mV
SPL: Battery Voltage = 4192mV
SPL: Battery Voltage too high
SPL: Configuring power block to boot from 5V input
SPL: 5V VDD good
SPL: Booting from 5V supply
SPL: Powering up 4P2 regulator
SPL: Configuring common 4P2 regulator params
SPL: Enabling 4P2 regulator
SPL: Charging 4P2 capacitor
SPL: Disabling 4P2 DC-DC Input
SPL: Setting 4P2 brownout level
SPL: Battery Voltage = 0mV
SPL: Switching DC-DC converters to 4P2
SPL: Enabling 4P2 DC-DC Input
SPL: 4P2 regulator powered-up
SPL: Switching CPU core clock source to PLL
SPL: Initialising battery brown-out level to 3.0V
SPL: Switching VDDD to DC-DC converters
SPL: Enabling output rail protection
SPL: Setting VDDIO to 3V3 (brownout @ 3v15)
SPL: Setting VDDD to 1V5 (brownout @ 1v315)
SPL: Initialising FRAC0
SPL: FRAC0 Initialised
SPL: Configuring VDDA
SPL: Initialising mx28 SDRAM Controller
SPL: Setting mx28 board specific SDRAM parameters
SPL: Applying SDRAM parameters
SPL: Setting CPU and HBUS clock frequencies


Но что самое интересное, через несколько попыток (иногда через 2-3 иногда через 30-40), U-boot загружается нормально:

...(вырезано)
SPL: Applying SDRAM parameters
SPL: Setting CPU and HBUS clock frequencies
LLCinitcall: 4007f918


U-Boot 2019.04-rc4 (Apr 05 2019 - 16:08:28 +0300)

initcall: 40017420
U-Boot code: 40002000 -> 400B1C6C  BSS: -> 400D4CA0
initcall: 40003414
CPU:   Freescale i.MX28 rev1.2 at 454 MHz
BOOT:  SSP SD/MMC #0, 3V3
initcall: 40017558
DRAM:  initcall: 40004940
initcall: 400176b0
Monitor len: 000D2CA0
Ram size: 08000000
Ram top: 48000000
initcall: 40017200
initcall: 40017254
TLB table from 47ff0000 to 47ff4000
initcall: 400175c0
initcall: 400175c8
initcall: 400173b8
Reserving 843k for U-Boot at: 47f1d000
initcall: 40017384
Reserving 4112k for malloc() at: 47b19000
initcall: 40017504
Reserving 80 Bytes for Board Info at: 47b18fb0
initcall: 40017218
initcall: 40017350
Reserving 184 Bytes for Global Data at: 47b18ef8
initcall: 400172c8
initcall: 400175d0
initcall: 400175d8
initcall: 40017600
initcall: 4001771c
initcall: 40017230
initcall: 40017614

RAM Configuration:
Bank #0: 40000000 128 MiB

DRAM:  128 MiB
initcall: 400172ac
New Stack Pointer is: 47b18ed0
initcall: 400174c0
initcall: 400175e0
initcall: 400175e8
initcall: 40017450
Relocation Offset is: 07f1b000
Relocating to 47f1d000, new gd at 47b18ef8, sp at 47b18ed0
initcall: 47f327e0
initcall: 47f327e8
initcall: 40017994 (relocated to 47f32994)
dram_bank_mmu_setup: bank: 0
initcall: 4001794c (relocated to 47f3294c)
efi_runtime_relocate: Relocating to offset=47f1d000
efi_runtime_relocate: rel->info=0x17 *p=0x40002800 rel->offset=40002478
efi_runtime_relocate: Setting 47f1d478 to 47f1d800
efi_runtime_relocate: rel->info=0x17 *p=0x40002798 rel->offset=40002768
efi_runtime_relocate: Setting 47f1d768 to 47f1d798
efi_runtime_relocate: rel->info=0x17 *p=0x400b015c rel->offset=40002774
efi_runtime_relocate: Setting 47f1d774 to 47fcb15c
efi_runtime_relocate: rel->info=0x17 *p=0x400b0198 rel->offset=4000277c
efi_runtime_relocate: Setting 47f1d77c to 47fcb198
efi_runtime_relocate: rel->info=0x17 *p=0x400b0198 rel->offset=40002784
efi_runtime_relocate: Setting 47f1d784 to 47fcb198
efi_runtime_relocate: rel->info=0x17 *p=0x400027b0 rel->offset=40002788
efi_runtime_relocate: Setting 47f1d788 to 47f1d7b0
efi_runtime_relocate: rel->info=0x17 *p=0x400b0070 rel->offset=4000278c
efi_runtime_relocate: Setting 47f1d78c to 47fcb070
efi_runtime_relocate: rel->info=0x17 *p=0x4006fd24 rel->offset=400027c8
efi_runtime_relocate: Setting 47f1d7c8 to 47f8ad24
efi_runtime_relocate: rel->info=0x17 *p=0x4000235c rel->offset=400027cc
efi_runtime_relocate: Setting 47f1d7cc to 47f1d35c
efi_runtime_relocate: rel->info=0x17 *p=0x40002354 rel->offset=400027d0
efi_runtime_relocate: Setting 47f1d7d0 to 47f1d354
efi_runtime_relocate: rel->info=0x17 *p=0x40002354 rel->offset=400027d4
efi_runtime_relocate: Setting 47f1d7d4 to 47f1d354
efi_runtime_relocate: rel->info=0x17 *p=0x4006fdd0 rel->offset=400027d8
efi_runtime_relocate: Setting 47f1d7d8 to 47f8add0
efi_runtime_relocate: rel->info=0x17 *p=0x40002364 rel->offset=400027dc
efi_runtime_relocate: Setting 47f1d7dc to 47f1d364
efi_runtime_relocate: rel->info=0x17 *p=0x400709b8 rel->offset=400027e0
efi_runtime_relocate: Setting 47f1d7e0 to 47f8b9b8
efi_runtime_relocate: rel->info=0x17 *p=0x40070e90 rel->offset=400027e4
efi_runtime_relocate: Setting 47f1d7e4 to 47f8be90
efi_runtime_relocate: rel->info=0x17 *p=0x400712e8 rel->offset=400027e8
efi_runtime_relocate: Setting 47f1d7e8 to 47f8c2e8
efi_runtime_relocate: rel->info=0x17 *p=0x4000235c rel->offset=400027ec
efi_runtime_relocate: Setting 47f1d7ec to 47f1d35c
efi_runtime_relocate: rel->info=0x17 *p=0x4006fc40 rel->offset=400027f0
efi_runtime_relocate: Setting 47f1d7f0 to 47f8ac40
efi_runtime_relocate: rel->info=0x17 *p=0x4000236c rel->offset=400027f4
efi_runtime_relocate: Setting 47f1d7f4 to 47f1d36c
efi_runtime_relocate: rel->info=0x17 *p=0x40002374 rel->offset=400027f8
efi_runtime_relocate: Setting 47f1d7f8 to 47f1d374
efi_runtime_relocate: rel->info=0x17 *p=0x4000237c rel->offset=400027fc
efi_runtime_relocate: Setting 47f1d7fc to 47f1d37c
initcall: 400179ac (relocated to 47f329ac)
initcall: 40017928 (relocated to 47f32928)
using memory 0x47b19000-0x47f1d000 for malloc()
initcall: 400171d0 (relocated to 47f321d0)
initcall: 40017914 (relocated to 47f32914)
initcall: 400179b4 (relocated to 47f329b4)
initcall: 400179a4 (relocated to 47f329a4)
initcall: 40004944 (relocated to 47f1f944)
initcall: 4006fac0 (relocated to 47f8aac0)
efi_add_memory_map: 0x40000000 0x8000 7 no
efi_add_memory_map: 0x46b18000 0x14e8 2 no
efi_add_memory_map: 0x47f1d000 0x1 5 no
initcall: 40023cfc (relocated to 47f3ecfc)
initcall: 40017904 (relocated to 47f32904)
initcall: 400178e8 (relocated to 47f328e8)
Now running in RAM - U-Boot at: 47f1d000
initcall: 400179bc (relocated to 47f329bc)
initcall: 400178b8 (relocated to 47f328b8)
NAND:  256 MiB
initcall: 40017898 (relocated to 47f32898)
MMC:   MXS MMC: 0
initcall: 40017868 (relocated to 47f32868)
Loading Environment from MMC... clock is disabled (0Hz)
MMC0: Set 0 bits bus width
SPI0: Set freq rate to 400 KHz (requested 400 KHz)
MMC0: Set 1 bits bus width
clock is enabled (400000Hz)
SPI0: Set freq rate to 400 KHz (requested 400 KHz)
MMC0: Set 1 bits bus width

Ревизия платы v1.1

В чем может быть причина...
« Последнее редактирование: 08 Апрель, 2019, 10:59:30 от OlegSL »

Оффлайн OlegSL

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Re: Сборка ванильного u-boot
« Ответ #1 : 17 Апрель, 2019, 13:56:13 »
Разобрался в чем было дело. Все, как обычно, дело в элементарных вещах, в SD-карте. Заменил на другую и все взлетело с первой раза.
Но нет худо без добра, попутно разобрался с debug'ом SPL и CST командами HAB i.MX28.

P.S. Если кому интересно от куда, при загрузке, в консоле появляются HTLLC - это как раз выполняются команды CST.
Более подробно о них можно прочитать в документации U-boot.